| IEEE Transactions on Very Large Scale Integration Systems |
A Unified and Low-Complexity Parallel Systolic Architecture for Both Multiplier and Squarer over GF(2^m) using Polynomial Basis |
第二作者 |
2005/12 |
| IEEE Trans. On Circuits and Systems I |
Efficient systolic arrays for power-sum, inversion, and division in GF(2^m) |
第一作者 |
2005/11 |
| IEE Proc. Computers & Digital Techniques |
Low-Complexity Bit-Parallel Systolic Architectures for Computing A(x)B^2(x) over GF(2^m) |
第二作者 |
2005/11 |
| IEICE Transactions on Fundamentals |
Efficient Design of Low-Complexity Bit-Parallel Systolic Hankel Multipliers To Implement multiplication in Normal and Dual Bases of GF(2m) |
第二作者 |
2005/11 |
| Journal of Electronic Testing: Theory and Applications |
Concurrent Error Detection In A Bit-Parallel Systolic Multiplier For Dual Basis Of GF(2m) |
第二作者 |
2005/10 |
| IEE Proceedings Communications |
Dynamic Resource Allocation for Handoff Using MC-CDMA in WATM Networks |
第二作者 |
2005/10 |
| International Journal of Electronics |
Low-Area Double-Basis Multipliers And Inverters Over GF(2^m) |
第二作者 |
2005/06 |
| International Journal of Electronics |
A Dual-Field Multiplier in GF(P) and GF(2^m) |
第一作者 |
2005/06 |
| International Journal of Computer Applications in Technology |
A Software Architectural Style for Migrating MS-Windows Applications Toward CORBA-based Software Systems |
第一作者 |
2005/06 |
| IEEE Transaction on Computers |
A Unified Low-Complexity Bit-Parallel Systolic Multiplier Architecture over GF(2^m) Using Hankel Matrix |
第二作者 |
2005/06 |
